1. Field of the Invention
The present invention relates to an improvement of a semiconductor integrated circuit memory device in which memory cells formed by integrated injection logic are arranged as a memory array.
2. Description of the Prior Art
Recently, a low power semiconductor memory or a high capacity semiconductor memory has been used. In conventional memory cells used in a semiconductor memory, resistors are used as load impedances of flip-flop transistors which are used in the memory cells, and also, an insulation between transistors is required, so that the conventional memory cells are large in size. Therefore, a memory chip is also large in size and the density of the memory chips which are included in one wafer can not be increased, so that the cost of a semiconductor memory is expensive.
For the purpose of obtaining memory cells having small dimensions, memory cells using integrated injection logic are used.
At present, memory cells which are constituted by integrated injection logic are elements of great importance, because such memory cells can be formed with high integration density. Such memory cells are disclosed, for example, in the articles "Write Current Control and Self Powering in a Low Power Memory Cell", IEEE, SSC, Jun., 1973, and "Superintegrated Memory Shares Functions on Diffused Islands", Electronics, Feb. 14, 1972, p83-p86. The former discloses a method of controlling a write current to the integrated injection logic memory cell and the latter discloses a basic idea with respect to the integrated injection logic memory cell.
As disclosed in the above mentioned articles, the integrated injection logic memory cell comprises a pair of first and second transistors which have emitters forming an injector which is connected to a word line W+, and said first and second transistors have emitters of a first conductivity type, a pair of third and fourth transistors which have a collector connected to a collector of the first or second transistors, a base of the third transistor which is connected to the collector of said fourth transistor and a base of the fourth transistor which is connected to the collector of said third transistor, and both said third and fourth transistors having emitters of a second, conductivity type opposite to said first type, and a bulk that is a word line W- which is connected to the bases of the first and second transistors and to emitters of the third and fourth transistors.
The integrated injection logic memory cells are arranged as the memory array. In these integrated injection logic memory cells, the word line W- is formed as the bulk, as already mentioned, and this bulk consists of two n type layers, an epitaxial layer and a buried layer. The epitaxial layer is formed on the buried layer which has a higher density of the impurity than the epitaxial layer. Therefore, the bulk, that is, the word line W- has a larger resistance than a metallic wire, and this resistance exists between each cell.
When the bulk is used as the word line W- which supplies the hold current, the characteristics of the cells are different in accordance with the positions of the cells in the line of the array.
That is, the following problems are caused in the memory device in which memory cells formed by integrated injection logic are arranged as a memory array.
(a) Deviation of a hold current
Since the word line W-, which is provided for supplying a hold current I.sub.H to each cell, has a resistance, the hold current which is supplied to the cell positioned farthest from the hold current supply transistor is small. The value of the hold current I.sub.H should be of sufficient value for holding the state of the cell which is at the most remote position from the hold current supply transistor. Therefore, an excess hold current is supplied to the cells positioned near the hold current supply transistor, so that excess power is dissipated in the memory device. Further, in accordance with the deviation of the hold current of the cell, the write characteristics of the cells are dependent on the position of the cells, because it is well known that a write threshold current to the cell is proportional to the injector current of the cell. A large injector current is supplied to the cell to which a large hold current is supplied. Therefore, the write threshold current of the cell near the hold current supply transistor increases.
(b) The write threshold current to the cell near the end of the memory array increases.
If, there is no deviation of the hold currents are illustrated in the above-item (a), the write threshold current to the cell near the end of the memory array increases. This is due to the reason that the write current flows also to non-selected cells, and this write current in the non-selected cell flows to the injector region of the cell. Therefore, the amount of the current shunted to the non-selected cell is different in accordance with whether or not the non-selected cells exist on both sides of the selected cell. Therefore, when only one non-selected cell exists at one side of the selected cell, the amount of the current shunted to the non-selected cell is small; therefore the current which flows in the selected cell as the injector current is large and the amount of the write threshold current also increases.
When we assume that the write current is constant, the increase of the write threshold current illustrated in the items (a) and (b) above results in an increase of the width of the minimum write pulse. The increases of the write threshold current and the width of the write pulse requires excess electrical power and also deteriorates the characteristics of the cells which are used as the random access memory.